1. Field of the Invention
This invention relates generally to superconducting memory cells which store information in the form of persistent circulating currents. More specifically, it relates to superconducting memory cells wherein stored binary information can be read out nondestructively (NDRO). Still more specifically, it relates to superconducting NDRO memory cells which incorporate only a single write gate in one of the pair of branches which forms a superconducting loop in such memory cells. Each of the pair of branches of the superconducting memory cell has a different value of inductance. The branch containing the single write gate may have the higher inductance and, to obtain the best sensing in such cells when the write gate I.sub.min = 0, it must be twice as great as the inductance of the other branch. In general the specific choice of the ratio of branch inductances is dependent upon I.sub.min. The write gate is a device capable of carrying Josephson current and may be a single or multijunction device which is capable of being switched by an associated control line. The multijunction devices are well-known to those skilled in the superconducting art as interferometers. To achieve the improved sensing of the present application, a sense gate in the form of another Josephson junction must be disposed in electromagnetically coupled relationship with the branch of the memory cell loop which does not contain the write gate. Finally, binary information must be stored in the resulting memory cell configuration in the form of clockwise and counterclockwise circulating currents of equal magnitude. Memory cells of the character just described retain information stored therein as long as the storage loops remain superconducting and have improved sensing margins over known NDRO memory cells. The criteria just outlined can be applied to all memory cells which store information in the form of counterrotating circulating currents and have application in regimes where coincident current writing or storage is carried out using single or multicontrol lines. Of course, such arrangements also utilize coincident current sensing. Memory cells of the character described can have a maximum Sense Discrimination Factor, F, of 3 irrespective of the magnitude of I.sub.min. By applying the teaching of the present application improvements in Sense Discrimination Factor, F, in the range of F's in excess of 2 to 3 can be achieved.
2. Description of the Prior Art
Memory cells using a single Josephson tunneling gate with counterrotating circulating currents to define two binary states and a sense gate associated with a branch of the memory cell loop not containing the write gate are well-known in the prior art. In the usual case, the inductances of the two branches of the loop are equal and, as a result, such cells cannot achieve the improved sense margins of the memory cell of the present application. Typical examples of such arrangements are shown in the following publications:
IBM Technical Disclosure Bulletin, Vol. 15, No. 2, July 1972, pp. 449-451, "Memory Cell Using a Single Josephson Gate" by W. Anacker.
IBM Technical Disclosure Bulletin, Vol. 15, No. 9, February 1973, pp. 2904-05, "NDRO Memory Cell Employing a Single Josephson Tunneling Gate" by W. Henkels.
Neither of the above memory cells can achieve the improved discrimination factor, F, of the present application because both of the cells call for superconducting loop branches of the same inductance.
Other known memories which incorporate circulating currents utilize the presence of only one circulating current to represent one binary condition and the absence of any circulating current to represent another binary condition. At least one is known which appears to have different values of inductance in the loop branches while another has nearly equal inductances in each branch. The following publications show one of each of these types:
IBM Technical Disclosure Bulletin, Vol. 16, No. 1, June 1973, p. 214, "Two Junction Josephson Memory" by P. Wolf. This publication appears to indicate a larger inductance in the branch containing the write gate although nothing is specifically mentioned in the publication with respect to that point. In any event, it does not specifically indicate any relationship between the values of the branch inductances. Beyond this, the cell does not use counterrotating circulating currents to indicate two possible binary states. In addition, the sense gate is associated with the same loop branch as the write gate.
IBM Technical Disclosure Bulletin, Vol. 17, No. 3, August 1974, pp. 890-1, "Nonvolatile, NDRO, Array Logic Memory Cell in Josephson Technology" by K. D. Terlep. Like the previous publication, the memory cell disclosed uses no circulating current to represent one of the binary states and has nearly equal inductances in each of the loop branches.
IBM Technical Disclosure Bulletin, Vol. 18, No. 11, April 1976, pp. 3852-53, "Josephson Feedback Memory Cells" by W. H. Henkels. This publication shows a Josephson memory cell with a single write gate and a sense gate disposed adjacent in a branch which does not contain the write gate. The inductances of the branches are equal and counterrotating circulating currents are utilized to represent the two binary conditions. The publication indicates that for a single-write-gate cell, the writing margins are independent of the ratio of inductances of the two branches. Other comments are made with respect to an ideal single cell to the effect that write margins can be increased by decreasing the value of K which in turn is a function of the inductances of the branches of the cell loop. It is further indicated that read margins have more complex dependencies. Finally, in the publication, it is indicated in the summary at the end of the article that "Cell asymmetry (K not equal to 1/2) may be used to advantage to increase margins, enabling the use of negligible self-field gates (low gain)." These general statements merely indicate that the inductances of the cell could be asymmetric but do not indicate any relationship between the write and sense gates nor do they suggest which value of inductance should be associated with the write gate to achieve either an improved or maximum discrimination factor.
Proceedings of the IEEE, April 1967, p. 592-3, "A Continuous Film Memory Driven by Multiple Coincident Pulses" by K. Goser et al. The memory array discussed in the article uses a triple coincident pulse memory cell. A separate decoder is utilized for x, y, and z drive lines. The article indicates that the approach utilized offers a considerable increase of the write operating range.
The foregoing prior art shows a number of single write gate NDRO memory cells and a memory array which utilizes a diagonal line driver in addition to the usual x and y drivers of memory arrays. The development of the single write gate memory cells shown appears to have focused on achieving good write margins with little attention being paid to the achievement of improved sense margins. Indeed, the best Sense Discrimination Factor, F, which can be achieved by the prior art is 2. Considering that many of the separate factors involved in achieving the present improved sense margins have been used in memory cell design for many years, it is submitted that the teaching of the present application is distinguishable and unobvious over all the references cited inasmuch as only one combination of a plurality of interacting factors can be utilized to achieve improved sense margins without affecting the write margins. It is clear from a consideration of the prior art that the knowledge of the separate factors involved was insufficient to lead to the improvement obtained using the teaching of the present application.